US 12,306,271 B2
Manufacturing method for fluxgate chip
Xiaowei Hou, Ningbo (CN); Yang Lv, Ningbo (CN); Liangguang Zheng, Ningbo (CN); Juping Li, Ningbo (CN); Po Zhang, Ningbo (CN); and Peng Wu, Ningbo (CN)
Assigned to NINGBO CRRC TIMES TRANSDUCER TECHNOLOGY CO., LTD., Ningbo (CN)
Appl. No. 18/000,846
Filed by NINGBO CRRC TIMES TRANSDUCER TECHNOLOGY CO., LTD., Ningbo (CN)
PCT Filed Jul. 15, 2020, PCT No. PCT/CN2020/102007
§ 371(c)(1), (2) Date Dec. 6, 2022,
PCT Pub. No. WO2021/248621, PCT Pub. Date Dec. 16, 2021.
Claims priority of application No. 202010509797.3 (CN), filed on Jun. 8, 2020.
Prior Publication US 2023/0213598 A1, Jul. 6, 2023
Int. Cl. G01R 33/00 (2006.01); G01R 33/04 (2006.01); G01R 33/3873 (2006.01)
CPC G01R 33/0052 (2013.01) [G01R 33/04 (2013.01); G01R 33/3873 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A manufacturing method for a fluxgate chip, comprising:
Step 1: selecting two high-resistance silicon wafers, electroplating a ferromagnetic core on a first surface of one of the two high-resistance silicon wafers, and performing etching on a first surface of the other high-resistance silicon wafer to form a ferromagnetic core cavity;
Step 2: bonding the high-resistance silicon wafer electroplated with the ferromagnetic core and the high-resistance silicon wafer with the ferromagnetic core cavity up and down to enable the ferromagnetic core to be inlaid in the ferromagnetic core cavity;
Step 3: performing oxidation treatment on a second surface of the high-resistance silicon wafer electroplated with the ferromagnetic core and a second surface of the high-resistance silicon wafer with the ferromagnetic core cavity to form insulating layers by deposition;
Step 4: etching multiple first coil grooves which crossing the ferromagnetic core and an independent first electrode window on the second surface of the high-resistance silicon wafer electroplated with the ferromagnetic core;
Step 5: in a thickness direction of the high-resistance silicon wafer electroplated with the ferromagnetic core, etching first through grooves communicated with the corresponding first coil grooves in two ends of each said first coil groove respectively;
Step 6: turning the two bonded high-resistance silicon wafers up and down;
Step 7: etching multiple second coil grooves which crossing the ferromagnetic core cavity and an independent second electrode window on the second surface of the high-resistance silicon wafer with the ferromagnetic core cavity;
Step 8: in a thickness direction of the high-resistance silicon wafer with the ferromagnetic core cavity, etching second through grooves communicated with the corresponding second coil grooves in two ends of each said second coil groove respectively, wherein the position of each second coil groove corresponds to the position of each first coil groove, the second through grooves are vertically communicated with the first through grooves and are coaxial with each other, such that an annular cavity is formed in the surface of the two high-resistance silicon wafers bonded up and down;
Step 9: performing oxidation treatment on surfaces of the first coil grooves, the first through grooves, the first electrode window, the second coil grooves, the second through grooves and the second electrode window to form insulating layers by deposition; and
Step 10: filling the annular cavity of the silicon wafer mold with alloy to form a solenoid coil, such that a fluxgate chip is manufactured.