US 12,306,112 B2
Methods and apparatus for detecting defects in semiconductor systems
Trevor A. Norman, Fremont, CA (US); Robert Mamazza, Palm Harbor, FL (US); and Francisco Xavier Machuca, Oakland, CA (US)
Assigned to AXIOMATIQUE TECHNOLOGIES, INC., Fremont, CA (US)
Filed by Axiomatique Technologies, Inc., Fremont, CA (US)
Filed on Jan. 12, 2021, as Appl. No. 17/147,317.
Application 17/147,317 is a continuation in part of application No. 17/073,042, filed on Oct. 16, 2020.
Prior Publication US 2022/0120698 A1, Apr. 21, 2022
Int. Cl. G01N 21/95 (2006.01); G01N 21/88 (2006.01); G01N 23/083 (2018.01); G01N 23/18 (2018.01); G06T 7/00 (2017.01)
CPC G01N 21/9501 (2013.01) [G01N 21/8806 (2013.01); G01N 23/083 (2013.01); G01N 23/18 (2013.01); G06T 7/0004 (2013.01); G06T 2207/30148 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A system comprising:
a light emitting device that outputs a light beam capable of penetrating a device under test at least to a first depth, the device under test comprising an advanced semiconductor package, wherein the light beam, upon initial output, comprises spatially coherent light waves, wherein the light emitting device comprises an incoherent light source and a light source attachment, wherein the light source attachment comprises a thin film waveguide and the light source attachment converts incoherent light waves emitted from the incoherent light source into spatially coherent light waves;
a detector that transforms light waves that were incident on the device under test into visible optical light, wherein the detector is placed between 10 millimeters and 1 meter away from the device under test;
wherein the detector is configured to:
generate, based on the visible optical light, one or more electronic maps indicating one or more concentrations or distributions of elements within the device under test,
cracks, breaks, gaps, or air pockets indicating one or more defects within the device under test based on Fresnel fringe interference patterns developed by the light waves, coordinates of the one or more defects, metering of physical extent or metrology to gauge repeatability or variances in physical dimensions of components or circuit elements within the device under test; and
wherein the one or more electronic maps comprises a plurality of squares representing at least one circuit element in the device under test.