US 11,985,865 B2
Display device including passivation layer with surface step and manufacturing method for the same
Byoung Kwon Choo, Hwaseong-si (KR); Seung Bae Kang, Suwon-si (KR); Bong Gu Kang, Seoul (KR); Tae Joon Kim, Seoul (KR); Jeong Min Park, Seoul (KR); Joon-Hwa Bae, Suwon-si (KR); Hee Sung Yang, Hwaseong-si (KR); and Woo Jin Cho, Yongin-si (KR)
Assigned to Samsung Display Co., Ltd., Yongin-Si (KR)
Filed by Samsung Display Co., Ltd., Yongin-Si (KR)
Filed on May 27, 2021, as Appl. No. 17/332,933.
Claims priority of application No. 10-2020-0114909 (KR), filed on Sep. 8, 2020.
Prior Publication US 2022/0077260 A1, Mar. 10, 2022
Int. Cl. H10K 59/123 (2023.01); H10K 50/84 (2023.01); H10K 50/86 (2023.01); H10K 59/12 (2023.01); H10K 59/38 (2023.01); H10K 59/40 (2023.01); H10K 71/00 (2023.01)
CPC H10K 59/123 (2023.02) [H10K 50/84 (2023.02); H10K 50/865 (2023.02); H10K 59/38 (2023.02); H10K 59/40 (2023.02); H10K 71/00 (2023.02); H10K 59/1201 (2023.02)] 6 Claims
OG exemplary drawing
 
1. A display device comprising:
a substrate;
a polycrystalline semiconductor that is disposed on the substrate;
a first gate insulation layer that is disposed on the polycrystalline semiconductor;
a driving gate electrode that is disposed on the first gate insulating layer;
a second gate insulating layer that is disposed on the driving gate electrode;
a first interlayer insulation layer that is disposed on the second gate insulating layer;
an oxide semiconductor that is disposed on the first interlayer insulating layer;
a third gate insulating layer that is disposed on the oxide semiconductor;
a switching gate electrode that is disposed on the third gate insulating layer;
a second interlayer insulating layer that is disposed on the switching gate electrode;
a first source electrode and a first drain electrode that are disposed on the second interlayer insulating layer, and connected with the oxide semiconductor;
a second source electrode and a second drain electrode that are disposed on the second interlayer insulating layer, and connected to the polycrystalline semiconductor;
a light emitting diode that is disposed on the substrate, and connected to the second source electrode or the second drain electrode; and
a passivation layer that is disposed between the second interlayer insulating layer and the light emitting diode,
wherein a surface step of the passivation layer is within a range of and including 1 nm to 30 nm,
wherein the passivation layer comprises a first portion that overlaps the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode, and a second portion that does not overlap the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode, and
wherein a surface height of the first portion is higher than a surface height of the second portion.