US 11,985,841 B2
Patterning a conductive deposited layer using a nucleation inhibiting coating and an underlying metallic coating
Michael Helander, Mississauga (CA); and Zhibin Wang, Mississauga (CA)
Assigned to OTI Lumionics Inc., Mississauga (CA)
Appl. No. 18/265,634
Filed by OTI Lumionics, Inc., Mississauga (CA)
PCT Filed Dec. 7, 2021, PCT No. PCT/IB2021/061385
§ 371(c)(1), (2) Date Jun. 6, 2023,
PCT Pub. No. WO2022/123431, PCT Pub. Date Jun. 16, 2022.
Claims priority of provisional application 63/122,421, filed on Dec. 7, 2020.
Claims priority of provisional application 63/129,163, filed on Dec. 22, 2020.
Claims priority of provisional application 63/141,857, filed on Jan. 26, 2021.
Prior Publication US 2023/0345757 A1, Oct. 26, 2023
Int. Cl. H01L 51/50 (2006.01); H10K 50/824 (2023.01); H10K 71/60 (2023.01); H10K 50/852 (2023.01)
CPC H10K 50/824 (2023.02) [H10K 71/60 (2023.02); H10K 50/852 (2023.02)] 82 Claims
OG exemplary drawing
 
1. A semiconductor device having a plurality of layers deposited on a substrate and extending in a first portion and a second portion of at least one lateral aspect defined by a lateral axis thereof, comprising:
an orientation layer comprising an orientation material, disposed on a first exposed layer surface of the device in at least the first portion;
at least one patterning layer comprising a patterning material, disposed on an exposed layer surface of the orientation layer; and
at least one deposited layer comprising a deposited material, disposed on a second exposed layer surface of the device in the second portion;
wherein the first portion is substantially devoid of a closed coating of the deposited material.