US 11,985,832 B1
Planar and trench capacitors with hydrogen barrier dielectric for logic and memory applications
Somilkumar J. Rathi, San Jose, CA (US); Noriyuki Sato, Hillsboro, OR (US); Niloy Mukherjee, San Ramon, CA (US); Rajeev Kumar Dokania, Beaverton, OR (US); Amrita Mathuriya, Portland, OR (US); Tanay Gosavi, Portland, OR (US); Pratyush Pandey, Kensington, CA (US); Jason Y. Wu, Albany, CA (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Dec. 15, 2021, as Appl. No. 17/552,323.
Application 17/552,323 is a continuation of application No. 17/550,899, filed on Dec. 14, 2021.
Int. Cl. H10B 53/30 (2023.01)
CPC H10B 53/30 (2023.02) 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first conductive interconnect and a second conductive interconnect within a first dielectric in a first level, the first conductive interconnect laterally separated from the second conductive interconnect; and
a second level above the first level, the second level comprising:
a first electrode structure on the first conductive interconnect and a second electrode structure on the second conductive interconnect, wherein the first electrode structure and the second electrode structure comprise:
a first conductive hydrogen barrier layer; and
a first conductive fill material on the first conductive hydrogen barrier layer;
an etch stop layer comprising an insulator, the etch stop layer laterally adjacent to the first electrode structure and the second electrode structure;
a first memory device comprising a first ferroelectric material or a first paraelectric material on least a portion of the first electrode structure, wherein the first memory device comprises a planar topography;
an encapsulation layer on the first memory device and on at least a portion of the etch stop layer;
a second dielectric on the encapsulation layer,
a via electrode on at least a portion of the first memory device, the via electrode comprising:
a second conductive hydrogen barrier layer comprising a lateral portion in contact with the first memory device and substantially vertical portions adjacent to the second dielectric; and
a second conductive fill material on the second conductive hydrogen barrier layer;
a third dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material adjacent to the second dielectric;
a trench within the third dielectric, the trench on the second electrode structure; and
a second memory device within the trench, the second memory device comprising:
a bottom electrode substantially conformal to a base and to a sidewall of the trench, and wherein the bottom electrode is in contact with the second electrode structure;
a dielectric layer substantially conformal to the bottom electrode wherein the dielectric layer comprises a second ferroelectric material or a second paraelectric material; and
a top electrode comprising in contact with the dielectric layer.