CPC H10B 43/27 (2023.02) [H01L 23/5226 (2013.01); H10B 43/10 (2023.02)] | 18 Claims |
1. A memory device, comprising:
a stacked structure;
a tubular element penetrating the stacked structure, wherein the tubular element comprises a dummy channel layer and a memory film, and the dummy channel layer is between the memory film and the conductive pillar;
a conductive pillar enclosed by the tubular element and extending beyond a bottom surface of the dummy channel layer;
memory cells in the stacked structure and electrically connected to the conductive pillar; and
a polycrystalline semiconductor layer below the memory cells, wherein the tubular element and the conductive pillar pass through the polycrystalline semiconductor layer, and a portion of an outer surface of the conductive pillar is covered by the tubular element.
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