US 11,985,821 B2
Semiconductor device with high integration
Young Jin Lee, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Nov. 14, 2019, as Appl. No. 16/684,245.
Application 16/684,245 is a division of application No. 15/687,178, filed on Aug. 25, 2017, granted, now 10,515,978.
Application 15/687,178 is a division of application No. 14/980,244, filed on Dec. 28, 2015, granted, now 9,780,114, issued on Oct. 3, 2017.
Claims priority of application No. 10-2015-0103965 (KR), filed on Jul. 22, 2015.
Prior Publication US 2020/0083251 A1, Mar. 12, 2020
Int. Cl. H10B 43/27 (2023.01); H10B 41/10 (2023.01); H10B 41/20 (2023.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01); H10B 43/20 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 41/10 (2023.02); H10B 41/20 (2023.02); H10B 43/10 (2023.02); H10B 43/20 (2023.02); H10B 41/27 (2023.02)] 8 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first slit insulating layer and a second slit insulating layer spaced apart from each other;
insulating layers stacked on top of each other and disposed between the first and second slit insulating layers;
conductive layers stacked on top of each other and interposed between the insulating layers, each of the conductive layers including a first portion adjacent to the first slit insulating layer, a second portion adjacent to the second slit insulating layer and a third portion between the first portion and the second portion;
pillars passing through the insulating layers and the conductive layers;
a barrier pattern interposed between each of the conductive layers and each of the insulating layers and extending between each of the conductive layers and each of the pillars;
a first deposition inhibiting pattern contacting the first slit insulating layer and interposed between the barrier pattern and the first portion in each of the conductive layers; and
a second deposition inhibiting pattern contacting the second slit insulating layer and interposed between the barrier pattern and the second portion in each of the conductive layers,
wherein the first deposition inhibiting pattern and the second deposition inhibiting pattern are spaced apart from each other by the third portion in each of the conductive layers, and
wherein the first portion, the second portion and the third portion in each of the conductive layers are connected to each other without interposing the first and second deposition inhibiting patterns.