CPC H04W 56/001 (2013.01) [H04L 5/0048 (2013.01); H04L 41/0803 (2013.01)] | 20 Claims |
1. A baseband processor configured to perform operations comprising:
configuring a discovery reference signal (DRS) window for synchronization signal block (SSB) transmission to a user equipment (UE);
transmitting a subCarrierSpacingCommon information element (IE) to the UE, wherein the subCarrierSpacingCommon IE is configured to indicate a number of SSB candidate positions for operation in the unlicensed spectrum above 6 gigahertz (Ghz);
determining that a channel in an unlicensed spectrum is not occupied; and
transmitting multiple SSBs to the UE in response to determining that the channel in the unlicensed spectrum is not occupied.
|