(1) randomly selecting, from R instructions, four groups of instructions and four groups of operands corresponding to the four groups of instructions, wherein the four groups of instructions are all 32-bit binary data, and the four groups of operands are all 64-bit binary data;

(2) accessing a supply voltage to the 32-bit RISC-V processor, wherein the supply voltage is a normal operating voltage of the 32-bit RISC-V processor, and the 32-bit RISC-V processor enters a normal operating state under the normal operating voltage, and an operating frequency of the 32-bit RISC-V processor at this moment is a normal operating frequency; sequentially loading the four groups of operands to a general register with a load instruction, sorting the four groups of instructions in chronological order, sequentially running the four groups of instructions and the corresponding four groups of operands according to the sorting order to successively obtain four normal information results corresponding to the four groups of instructions, and storing the four normal information results in the general register, wherein the four normal information results are 32-bit binary data;

(3) decreasing the supply voltage accessed to the 32-bit RISC-V processor to 0.7V, wherein the supply voltage at this moment is an abnormal operating voltage of the 32-bit RISC-V processor, and the 32-bit RISC-V processor enters an abnormal operating state under the abnormal operating voltage;

(4) acquiring a current operating temperature of the 32-bit RISC-V processor from the temperature sensor, acquiring a current operating voltage of the 32-bit RISC-V processor from the voltage sensor, denoting the current operating temperature of the 32-bit RISC-V processor as temp_cur, denoting the current operating voltage of the 32-bit RISC-V processor as V_cur, and obtaining a compensatory operating frequency of the 32-bit RISC-V processor by calculation according to formula (1):

In formula (1), temp_ref is a reference temperature of the 32-bit RISC-V processor ((temp_ref=25° C.), V_ref is a reference voltage of the 32-bit RISC-V processor (V_ref=0.7V), F_ref is the normal operating frequency of the 32-bit RISC-V processor, F_com is the compensatory operating frequency of the 32-bit RISC-V processor, a_temp is a temperature compensation coefficient of the 32-bit RISC-V processor and is determined by testing the fluctuation velocity of a delay of the 32-bit RISC-V processor with time under different temperatures, a_vdd is a voltage compensation coefficient of the 32-bit RISC-V processor and is determined by testing the fluctuation velocity of the delay of the 32-bit RISC-V processor with voltage under different supply voltages, and In is a logarithmic operator;

(5) setting the operating frequency of the 32-bit RISC-V processor as the compensatory operating frequency;

(6) loading the four groups of operands to the general register again with the load instruction, then sequentially running the four groups of instructions and the corresponding four groups of operands in chronological order the same as that in Step (2) to successively obtain four abnormal information results corresponding to the four groups of instructions, and storing the four abnormal information results in the general register, wherein the four abnormal information results are 32-bit binary data;

(7) bitwise comparing the normal information results and the abnormal information results corresponding to the four groups of instructions one by one to determine error bits of the abnormal information result corresponding to each group of instructions with respect to the normal information result corresponding to the group of instructions, calculating the number of the error bits, and then converting the number of the error bits into 5-bit binary data, so that four pieces of 5-bit binary data corresponding to the four groups of instructions are obtained; and

(8) sequentially stitching the four pieces of 5-bit binary data from high bit to low bit according to a corresponding instruction running order to obtain 20-bit binary data, wherein the 20-bit binary data is the output response of the software PUF.