US 11,985,068 B2
Dynamic load balancing for multi-core computing environments
Stephen Palermo, Chandler, AZ (US); Bradley Chaddick, Portland, OR (US); Gage Eads, Austin, TX (US); Mrittika Ganguli, Tempe, AZ (US); Abhishek Khade, Chandler, AZ (US); Abhirupa Layek, Chandler, AZ (US); Sarita Maini, Tempe, AZ (US); Niall McDonnell, Limerick (IE); Rahul Shah, Chandler, AZ (US); Shrikant Shah, Chandler, AZ (US); William Burroughs, Macungie, PA (US); and David Sonnier, Austin, TX (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 13, 2023, as Appl. No. 18/154,619.
Application 18/154,619 is a continuation of application No. 17/018,809, filed on Sep. 11, 2020, granted, now 11,575,607.
Claims priority of provisional application 62/979,963, filed on Feb. 21, 2020.
Claims priority of provisional application 62/899,061, filed on Sep. 11, 2019.
Prior Publication US 2023/0231809 A1, Jul. 20, 2023
Int. Cl. H04L 47/125 (2022.01); H04L 47/62 (2022.01); H04L 47/625 (2022.01); H04L 47/6275 (2022.01)
CPC H04L 47/125 (2013.01) [H04L 47/62 (2013.01); H04L 47/624 (2013.01); H04L 47/6255 (2013.01); H04L 47/6275 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor die comprising:
a first core and a second core; and
circuitry in the semiconductor die, the circuitry separate from the first core and the second core, the circuitry to:
assign the first core to process first data packets of a data flow, the first core to execute one or more operations on the first data packets to produce processed first data packets;
assign the second core to process second data packets of the data flow based on a size of the data flow, the second core to execute the one or more operations on the second data packets to produce processed second data packets; and
re-order the processed first data packets and the processed second data packets to produce a processed data flow.