	US 11,984,979 B1
	Techniques for mapping coded bits to different channel reliability levels for low density parity check codes
Pinar Sen, San Diego, CA (US); Wei Yang, San Diego, CA (US); and Jing Jiang, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Jan. 17, 2023, as Appl. No. 18/155,437.
Int. Cl. H04L 1/18 (2023.01); H04L 1/00 (2006.01)

CPC H04L 1/0063 (2013.01) [H04L 1/0009 (2013.01); H04L 1/0071 (2013.01)]

30 Claims

1. An apparatus for wireless communication at a wireless device, comprising:

at least one processor; and

memory coupled with the at least one processor, the memory storing instructions for the at least one processor to cause the wireless device to:

generate a parity check matrix based at least in part on performing a lifting operation on a base matrix, wherein each column of the base matrix corresponds to a different variable node and each row corresponds to a different check node;

generate a set of coded bits based at least in part on the parity check matrix, wherein the set of coded bits comprises a set of data bits and a set of parity bits and each coded bit of the set of coded bits is associated with a respective variable node;

interleave the set of coded bits such that subsets of the set of coded bits associated with a same variable node are mapped to a same channel reliability level; and

transmit the set of coded bits according to the interleaving.