at least one processor, and

at least one memory for storing instructions to be executed by the processor, wherein the at least one memory and the instructions are configured to, with the at least one processor, cause the apparatus at least to perform:

maintaining, in said at least one memory, information on a reference incidence direction and reference configuration information defining a plurality of configurations of a plurality of tunable load impedance circuits of a tunable reflective array of a reconfigurable intelligent surface or a subpanel thereof for implementing a plurality of different reflection beams when reception occurs from the reference incidence direction;

maintaining, in said at least one memory, a plurality of beam codebooks defining a plurality of sets of beamforming coefficients for the tunable reflective array, wherein the plurality of sets of beamforming coefficients define at least phases inducible by the plurality of tunable load impedance circuits for implementing the plurality of different reflection beams;

measuring an incidence direction from which electromagnetic waves are received by the reconfigurable intelligent surface;

calculating, based on the reference incidence direction, the measured incidence direction and the reference configuration information, corrected configuration information, which defines a plurality of corrected configurations of the plurality of tunable load impedance circuits for implementing the plurality of different reflection beams when reception occurs from the measured incidence direction, by calculating a correction matrix based on the reference incidence direction and the measured incidence direction, wherein the correction matrix defines a plurality of correction coefficients for the plurality of sets of beamforming coefficients, and by calculating the plurality of corrected configurations of the plurality of tunable load impedance circuits based on the plurality of beam codebooks and the correction matrix; and

configuring the plurality of tunable load impedance circuits according to a corrected configuration defined in the corrected configuration information.