US 11,984,905 B2
High-speed and low-power successive approximation register analog-to-digital converter (SAR ADC) and analog-to-digital conversion method
Zhixiang Huang, Hefei (CN); Xueshi Hou, Hefei (CN); Zongming Duan, Hefei (CN); Bowen Wu, Hefei (CN); and Jiecheng Zhao, Hefei (CN)
Assigned to Anhui University, Hefel (CN)
Filed by Anhui University, Hefei (CN)
Filed on Jun. 23, 2022, as Appl. No. 17/847,409.
Claims priority of application No. 202210384574.8 (CN), filed on Apr. 13, 2022.
Prior Publication US 2023/0336184 A1, Oct. 19, 2023
Int. Cl. H03M 1/10 (2006.01)
CPC H03M 1/1014 (2013.01) 18 Claims
OG exemplary drawing
 
1. A high-speed and low-power successive approximation register analog-to-digital converter (SAR ADC), comprising a sample and hold circuit, a binarization circuit, and a digital error correction circuit; wherein
the sample and hold circuit is configured to sample an input signal to obtain a sampled signal;
the binarization circuit is connected to an output terminal of the sample and hold circuit; the binarization circuit comprises a digital-to-analog converter (DAC) capacitor array, the DAC capacitor array comprises two capacitor sub-arrays with a same structure, the capacitor sub-arrays each comprise a plurality of capacitors, a lower plate of each of the capacitors is selectively connected to a reference voltage, a ground, or the sampled signal through a multiplexer switch, and upper plates of all of the capacitors are connected to serve as an output terminal of the capacitor sub-array; and the total number of capacitors comprised in the capacitor sub-array is greater than the number of precision bits of the SAR ADC, and the total number of unit capacitors comprised in all of the capacitors when the total number of capacitors comprised in the capacitor sub-array is greater than the number of precision bits of the SAR ADC is equal to the total number of unit capacitors comprised in all of the capacitors when the total number of capacitors comprised in the capacitor sub-array is equal to the number of precision bits of the SAR ADC;
the binarization circuit is configured to binarize the sampled signal to obtain an initial binary code; and a number of bits of the initial binary code is equal to the total number of capacitors comprised in the capacitor sub-array; and
the digital error correction circuit is connected to an output terminal of the binarization circuit; the digital error correction circuit is configured to convert the initial binary code to obtain a binary code; and a number of bits of the binary code is equal to the number of precision bits of the SAR ADC.