CPC H03M 1/0626 (2013.01) [G06F 3/044 (2013.01); H03H 7/0161 (2013.01); H03M 1/1245 (2013.01); H03M 3/462 (2013.01); G06F 3/041 (2013.01)] | 5 Claims |
1. A digital decimation filtering circuit of an analog to digital conversion circuit, the digital decimation filtering circuit comprises:
an n-tap anti-aliasing filter operable to:
receive a 1-bit analog to digital converter (ADC) output signal at an oversampling rate; and
filter the 1-bit ADC output signal to remove frequencies higher than a selected cut-off frequency to produce an n-bit filtered signal at a first data output rate; and
a decimator operable to:
receive the n-bit filtered signal at the first data output rate;
decimate the n-bit filtered signal by a decimation factor to produce a set of output signals; and
sum the set of outputs to produce a decimated signal at a second data output rate, wherein the first data output rate is greater than the second data output rate.
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