US 11,984,901 B2
Compensation circuit and method for frequency divider circuit
Mao-Hsuan Chou, Hsinchu (TW); Chih-Hsien Chang, Hsinchu (TW); and Ruey-Bin Sheen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on May 31, 2022, as Appl. No. 17/829,044.
Application 17/829,044 is a continuation of application No. 17/172,046, filed on Feb. 9, 2021, granted, now 11,374,584.
Application 17/172,046 is a continuation of application No. 16/597,295, filed on Oct. 9, 2019, granted, now 10,924,125, issued on Feb. 16, 2021.
Claims priority of provisional application 62/749,461, filed on Oct. 23, 2018.
Prior Publication US 2022/0294460 A1, Sep. 15, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H03L 7/099 (2006.01)
CPC H03L 7/0992 (2013.01) 20 Claims
OG exemplary drawing
 
1. A method, comprising:
generating a counter signal counting at a frequency of a clock signal;
selecting, among a plurality of different numeric ranges corresponding to a plurality of different thresholds, a threshold corresponding to a numeric range containing a frequency ratio; and
in response to the counter signal reaching the selected threshold, switching a logic level of an output signal.