US 11,984,534 B2
Process for producing a semiconductor component based on a III-N compound
Jean Rottner, Grenoble (FR); and Helge Haas, Grenoble (FR)
Assigned to Commissariat à l'Energie Atomique et aux Energies Alternatives, Paris (FR)
Appl. No. 17/309,710
Filed by Commissariat à l'Energie Atomique et aux Energies Alternatives, Paris (FR)
PCT Filed Dec. 18, 2019, PCT No. PCT/FR2019/053174
§ 371(c)(1), (2) Date Jun. 16, 2021,
PCT Pub. No. WO2020/128339, PCT Pub. Date Jun. 25, 2020.
Claims priority of application No. 1873668 (FR), filed on Dec. 20, 2018.
Prior Publication US 2022/0037560 A1, Feb. 3, 2022
Int. Cl. H01L 29/00 (2006.01); H01L 21/02 (2006.01); H01L 29/20 (2006.01); H01L 33/00 (2010.01); H01L 33/32 (2010.01)
CPC H01L 33/32 (2013.01) [H01L 21/0206 (2013.01); H01L 29/2003 (2013.01); H01L 33/0075 (2013.01); H01L 33/0095 (2013.01)] 9 Claims
OG exemplary drawing
 
1. Method of manufacturing a semiconductor component, comprising the successive steps of:
a) forming a stack comprising a first semiconductor layer made of a III-N compound, a second conductive layer coating the first semiconductor layer, and a third hard mask layer coating the second layer;
b) forming a trench crossing the third hard mask layer and second conductive layer and stopping on the first semiconductor layer, said trench laterally delimiting a contact metallization in the second conductive layer;
c) forming in said trench a metal spacer made of a material different from that of the second conductive layer, in contact with the sides of the third hard mask layer and the second conductive layer, wherein said forming comprises a step of deposition of a metal layer made of said material different from that of the second conductive layer on the upper surface of the third hard mask layer and on the lateral walls and at the bottom of said trench, then a step of vertical anisotropic etching of the metal layer, at the end of which only the vertical portions of the metal layer coating the lateral walls of said trench are kept; and
d) continuing said trench through at least a portion of the thickness of the first semiconductor layer.