US 11,984,512 B2
Memory structure for self-erasing secret storage
Uri Bear, Pardes-Hana (IL); Elad Peer, Yokneam Ilit (IL); Elena Sidorov, Haifa (IL); Rami Sudai, Haifa (IL); Reuven Elbaum, Haifa (IL); and Steve J. Brown, Phoenix, AZ (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 25, 2020, as Appl. No. 17/033,444.
Prior Publication US 2021/0020775 A1, Jan. 21, 2021
Int. Cl. H01L 29/788 (2006.01); G11C 16/04 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H10B 41/00 (2023.01); H10B 43/00 (2023.01)
CPC H01L 29/788 (2013.01) [G11C 16/0408 (2013.01); H01L 29/42324 (2013.01); H01L 29/66825 (2013.01); H10B 41/00 (2023.02); H10B 43/00 (2023.02)] 10 Claims
OG exemplary drawing
 
1. A system comprising:
a processor coupled to a memory, the memory comprising at least one non-volatile memory cell that is configured to store a charge in a gate and have a retention time that is within a statistical window around a selected lifespan, wherein the gate includes a control gate, and wherein the non-volatile memory cell is stressed by applying cycles of high voltage to the control gate of the non-volatile memory such that the charge is set to leak and continue to leak based on a predetermined amount or percentage over a predetermined amount of time based on the selected lifespan.