US 11,984,485 B2
Semiconductor device, FinFET device and methods of forming the same
Po-Hsien Cheng, Hsinchu (TW); Jr-Hung Li, Hsinchu County (TW); Tai-Chun Huang, Hsin-Chu (TW); Tze-Liang Lee, Hsinchu (TW); Chung-Ting Ko, Kaohsiung (TW); Jr-Yu Chen, Taipei (TW); and Wan-Chen Hsieh, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 3, 2022, as Appl. No. 17/685,401.
Application 17/685,401 is a continuation of application No. 16/805,862, filed on Mar. 2, 2020, granted, now 11,271,083.
Claims priority of provisional application 62/906,745, filed on Sep. 27, 2019.
Prior Publication US 2022/0238669 A1, Jul. 28, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/417 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/41791 (2013.01) [H01L 29/0847 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01); H01L 2029/7858 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate having an active region and an isolation structure aside the active region;
a gate structure on the substrate;
a source/drain (S/D) region, located in the substrate and on a side of the gate structure;
a silicide layer, disposed on the S/D region and in contact with a top surface of the isolation structure;
a contact landing on the silicide layer and connected to the S/D region, wherein the contact wraps around the silicide layer and S/D region and is in contact with the top surface of the isolation structure; and
an additional dielectric layer, disposed on the substrate and laterally aside the contact, wherein the contact comprises a lower portion in contact with the top surface of the isolation structure, and the lower portion of the contact layer is in contact with the additional dielectric layer.