US 11,984,466 B2
Solid-state imaging element and video recording apparatus
Akiko Honjo, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Appl. No. 17/298,875
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Nov. 14, 2019, PCT No. PCT/JP2019/044659
§ 371(c)(1), (2) Date Jun. 1, 2021,
PCT Pub. No. WO2020/121725, PCT Pub. Date Jun. 18, 2020.
Claims priority of application No. 2018-233437 (JP), filed on Dec. 13, 2018.
Prior Publication US 2022/0059595 A1, Feb. 24, 2022
Int. Cl. H01L 27/146 (2006.01); H04N 25/76 (2023.01)
CPC H01L 27/14634 (2013.01) [H01L 27/14614 (2013.01); H01L 27/14636 (2013.01); H01L 27/14641 (2013.01); H01L 27/14643 (2013.01); H04N 25/76 (2023.01)] 6 Claims
OG exemplary drawing
 
1. A solid-state imaging element comprising:
a first semiconductor substrate that includes a floating diffusion that temporarily holds an electric signal output from a photoelectric conversion element; and
a second semiconductor substrate that faces the first semiconductor substrate, wherein
the second semiconductor substrate includes:
a first transistor disposed on a side facing the first semiconductor substrate, the first transistor including:
a channel extending along a thickness direction of the second semiconductor substrate; and
a multi-gate extending along the thickness direction of the second semiconductor substrate and sandwiching the channel, wherein the multi-gate of the first transistor is connected to the floating diffusion;
a source region that extends from one surface side of the second semiconductor substrate and reaches another surface side of the second semiconductor substrate,
wherein the one surface side of the second semiconductor substrate is opposite the another surface side of the second semiconductor substrate, and
wherein the another surface side of the second semiconductor substrate faces the first semiconductor substrate; and
a drain region that extends from the one surface side of the second semiconductor substrate and reaches the another surface side of the second semiconductor substrate,
wherein the source region is connected to a signal line that transmits the electric signal from the one surface side of the second semiconductor substrate, and
wherein the drain region is connected to a power supply potential from the one surface side of the second semiconductor substrate.