	US 11,984,433 B2
	Arrangements of power semiconductor devices for improved thermal performance
Brice McPherson, Fayetteville, AR (US); Benjamin A. Samples, Fayetteville, AR (US); and Brandon Passmore, Fayetteville, AR (US)
Assigned to Wolfspeed, Inc., Durham, NC (US)
Filed by Wolfspeed, Inc., Durham, NC (US)
Filed on Aug. 27, 2021, as Appl. No. 17/459,497.
Prior Publication US 2023/0060641 A1, Mar. 2, 2023
Int. Cl. H01L 25/07 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01)

CPC H01L 25/072 (2013.01) [H01L 25/18 (2013.01); H01L 25/50 (2013.01)]

33 Claims

1. A power module comprising:

a substrate; and

a plurality of power semiconductor devices on the substrate, wherein the plurality of power semiconductor devices are electrically coupled to form at least a portion of a power circuit, wherein:

the plurality of power semiconductor devices are arranged in at least one row; and

first next-adjacent power semiconductor devices of the plurality of power semiconductor devices are arranged along the at least one row with a spacing therebetween different from a spacing between second next-adjacent power semiconductor devices of the plurality of power semiconductor devices arranged along the at least one row.