US 11,984,427 B2
Mitigating thermal impacts on adjacent stacked semiconductor devices
Sui Chi Huang, Taichung (TW)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Oct. 7, 2022, as Appl. No. 17/962,258.
Application 17/962,258 is a division of application No. 16/871,490, filed on May 11, 2020, granted, now 11,469,207.
Prior Publication US 2023/0033685 A1, Feb. 2, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 21/67 (2006.01); H01L 23/34 (2006.01); H01L 23/40 (2006.01)
CPC H01L 25/0652 (2013.01) [H01L 21/67098 (2013.01); H01L 23/34 (2013.01); H01L 23/4012 (2013.01); H01L 2225/06589 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A method for managing thermal energy, comprising:
applying thermal energy from a thermal component to a first set of stacked semiconductor devices of a semiconductor device assembly; and
absorbing, by a temperature adjusting component of the semiconductor device assembly, at least a portion of thermal energy generated by the thermal component such that the portion of thermal energy is inhibited from increasing a temperature of a second set of stacked semiconductor devices based at least in part on the temperature adjusting component contacting a substrate of the semiconductor device assembly on a side opposite the second set of stacked semiconductor devices in a region at least partially vertically aligned with the second set of stacked semiconductor devices and excluding any region vertically aligned with the first set of stacked semiconductor devices.