US 11,984,421 B2
Integrated circuit chip having BS-PDN structure
Eunseok Song, Hwaseong-si (KR); Hongjoo Baek, Seongnam-si (KR); Kyungsuk Oh, Seongnam-si (KR); Manho Lee, Hwaseong-si (KR); and Hyuekjae Lee, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Apr. 12, 2021, as Appl. No. 17/228,111.
Claims priority of application No. 10-2020-0145241 (KR), filed on Nov. 3, 2020.
Prior Publication US 2022/0139863 A1, May 5, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01)
CPC H01L 24/24 (2013.01) [H01L 23/3157 (2013.01); H01L 23/481 (2013.01); H01L 23/5286 (2013.01); H01L 2224/24265 (2013.01); H01L 2924/19041 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit chip comprising:
a substrate having an active surface and a back surface opposite to the active surface;
a front-end-of-line (FEOL) structure disposed on the active surface of the substrate;
a first back-end-of-line (BEOL) structure disposed on the FEOL structure;
an intermediate connection layer disposed under the back surface of the substrate, the intermediate connection layer comprising a charge storage, and metal posts disposed around the charge storage; and
a re-distribution structure layer disposed under the intermediate connection layer,
wherein a top surface of the charge storage, that faces towards the substrate, is a part of a top surface of the intermediate connection layer, or the top surface of the charge storage is directly connected to a connection pad within the intermediate connection layer.