US 11,984,403 B2
Integrated substrate structure, redistribution structure, and manufacturing method thereof
Dyi-Chung Hu, Hsinchu (TW)
Filed by Dyi-Chung Hu, Hsinchu (TW)
Filed on Sep. 17, 2020, as Appl. No. 17/024,676.
Claims priority of provisional application 62/935,641, filed on Nov. 15, 2019.
Prior Publication US 2021/0151382 A1, May 20, 2021
Int. Cl. H01L 23/532 (2006.01); B23K 1/00 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 21/60 (2006.01)
CPC H01L 23/53242 (2013.01) [B23K 1/00 (2013.01); H01L 21/4853 (2013.01); H01L 23/53228 (2013.01); H01L 24/14 (2013.01); H01L 2021/60135 (2013.01)] 10 Claims
OG exemplary drawing
 
1. An integrated substrate structure configured to be testable prior to a semiconductor die assembly, comprising:
a redistribution film comprising a fine redistribution circuitry, wherein the fine redistribution circuitry includes a plurality of conductive pads at a bottom surface of the redistribution film;
a circuit substrate disposed over the redistribution film and comprising a core layer and a coarse redistribution circuitry disposed in and on the core layer, wherein the circuit substrate is thicker and more rigid than the redistribution film, and a layout density of the fine redistribution circuitry is denser than that of the coarse redistribution circuitry;
a plurality of conductive features interposed between the circuit substrate and the redistribution film to be connected to the fine redistribution circuitry and the coarse redistribution circuitry;
a surface finishing layer disposed on the plurality of conductive pads; and
a plurality of external terminals disposed on and electrically connected to the surface finishing layer,
wherein the surface finishing layer is placed to avoid oxidation and protect a surface of the plurality of conductive pads, a material of the surface finishing layer includes nickel, palladium, gold, or a combination thereof, and sidewalls of the surface finishing layer are exposed from the redistribution film.