US 11,984,396 B2
Localized high density substrate routing
Robert Starkston, Phoenix, AZ (US); Debendra Mallik, Chandler, AZ (US); John S. Guzek, Chandler, AZ (US); Chia-Pin Chiu, Tempe, AZ (US); Deepak Kulkarni, Chandler, AZ (US); and Ravi V. Mahajan, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 27, 2022, as Appl. No. 18/089,213.
Application 14/818,902 is a division of application No. 13/630,297, filed on Sep. 28, 2012, granted, now 9,136,236, issued on Sep. 15, 2015.
Application 18/089,213 is a continuation of application No. 17/972,340, filed on Oct. 24, 2022.
Application 17/972,340 is a continuation of application No. 17/009,308, filed on Sep. 1, 2020, granted, now 11,515,248, issued on Nov. 29, 2022.
Application 17/009,308 is a continuation of application No. 16/002,740, filed on Jun. 7, 2018, granted, now 10,796,988, issued on Oct. 6, 2020.
Application 16/002,740 is a continuation of application No. 15/620,555, filed on Jun. 12, 2017, granted, now 10,366,951, issued on Jul. 30, 2019.
Application 15/620,555 is a continuation of application No. 15/049,500, filed on Feb. 22, 2016, granted, now 9,679,843, issued on Jun. 13, 2017.
Application 15/049,500 is a continuation of application No. 14/818,902, filed on Aug. 5, 2015, granted, now 9,269,701, issued on Feb. 23, 2016.
Prior Publication US 2023/0130944 A1, Apr. 27, 2023
Int. Cl. H01L 23/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC H01L 23/5226 (2013.01) [H01L 23/5385 (2013.01); H01L 24/06 (2013.01); H01L 24/14 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01); H01L 21/563 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 25/18 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05541 (2013.01); H01L 2224/05568 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/131 (2013.01); H01L 2224/1403 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/83102 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/15192 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a medium having an interconnect in an insulating layer, the interconnect above a conductive line;
an interconnect element above the medium, the interconnect element having electrically conductive pads thereon, and the interconnect element comprising a silicon die, wherein the interconnect element is vertically over and spaced apart from the conductive line of the medium;
a conductive structure laterally spaced apart from the interconnect element, the conductive structure vertically over and electrically coupled to the interconnect of the medium;
an insulator material on the insulating layer of the medium, the insulator material laterally adjacent to the interconnect element, and the insulator material in lateral contact with the conductive structure, wherein the insulator material is vertically over and spaced apart from the conductive line of the medium;
a first die over the interconnect element, the first die coupled to a first of the electrically conductive pads of the interconnect element, and the first die electrically coupled to the conductive structure; and
a second die over the interconnect element, the second die coupled to a second of the electrically conductive pads of the interconnect element.