US 11,984,360 B2
Method for producing a diode
Gregory Avenier, Saint Nazaire les Eymes (FR); Alexis Gauthier, Meylan (FR); and Pascal Chevalier, Chapareillan (FR)
Assigned to STMicroelectronics (Crolles 2) SAS, Crolles (FR)
Filed by STMicroelectronics (Crolles 2) SAS, Crolles (FR)
Filed on Apr. 25, 2022, as Appl. No. 17/728,088.
Application 17/728,088 is a division of application No. 16/909,333, filed on Jun. 23, 2020, granted, now 11,348,834.
Claims priority of application No. 1907150 (FR), filed on Jun. 28, 2019.
Prior Publication US 2022/0254686 A1, Aug. 11, 2022
Int. Cl. H01L 21/82 (2006.01); H01L 21/3105 (2006.01); H01L 21/8222 (2006.01); H01L 21/8249 (2006.01); H01L 27/06 (2006.01); H01L 29/66 (2006.01); H01L 29/737 (2006.01); H01L 29/93 (2006.01)
CPC H01L 21/8222 (2013.01) [H01L 21/31056 (2013.01); H01L 21/8249 (2013.01); H01L 27/0664 (2013.01); H01L 29/66174 (2013.01); H01L 29/66242 (2013.01); H01L 29/7371 (2013.01); H01L 29/93 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A method, comprising jointly producing a bipolar transistor and a variable capacitance diode on a common substrate, wherein jointly producing comprises:
forming an insulating layer over the common substrate;
forming a conductive layer over the insulating layer;
forming a first opening extending through the conductive and insulating layers;
forming a second opening extending through the conductive and insulating layers;
simultaneously forming an intrinsic base of the bipolar transistor and a diode node of the variable capacitance diode;
wherein simultaneously forming comprises forming the diode node of the variable capacitance diode in the first opening at the insulating layer and forming the intrinsic base of the bipolar transistor in the second opening at the insulating layer;
depositing a sacrificial layer over the diode node of the variable capacitance diode and over the intrinsic base of the bipolar transistor;
forming spacers from the deposited sacrificial layer within the second opening over the intrinsic base of the bipolar transistor; and
then forming an emitter of the bipolar transistor over the intrinsic base while the diode node of the variable capacitance diode is covered by the sacrificial layers;
wherein the emitter of the bipolar transistor is positioned between the spacers and in contact with the intrinsic base.