US 11,984,359 B2
Semiconductor device with spacers for self aligned vias
Pokuan Ho, Taipei (TW); Hsin-Ping Chen, Hsinchu County (TW); and Chia-Tien Wu, Taichung (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, Hsin-Chu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, Hsin-Chu (TW)
Filed on Feb. 28, 2022, as Appl. No. 17/682,688.
Application 17/682,688 is a division of application No. 16/669,917, filed on Oct. 31, 2019, granted, now 11,264,277.
Prior Publication US 2022/0181207 A1, Jun. 9, 2022
Int. Cl. H01L 21/768 (2006.01); H01L 23/522 (2006.01)
CPC H01L 21/76897 (2013.01) [H01L 21/7681 (2013.01); H01L 21/76834 (2013.01); H01L 21/76847 (2013.01); H01L 23/5226 (2013.01); H01L 2221/1026 (2013.01); H01L 2224/05006 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor device, comprising:
forming a first dielectric structure and a second dielectric structure, wherein a conductive structure and a sacrificial material structure are disposed between the first dielectric structure and the second dielectric structure;
removing a portion of the first dielectric structure to define a first recess;
forming a spacer structure in the first recess;
removing at least some of the sacrificial material structure to define a second recess;
forming a dielectric layer over the spacer structure and in the second recess;
removing some of the dielectric layer to define a third recess and expose the spacer structure; and
forming a metal layer in the third recess.