US 11,984,357 B2
Semiconductor structure and its manufacturing method
BingYu Zhu, Hefei (CN); Hai-Han Hung, Hefei (CN); and Yin-Kuei Yu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Oct. 19, 2021, as Appl. No. 17/504,800.
Application 17/504,800 is a continuation of application No. PCT/CN2021/103800, filed on Jun. 30, 2021.
Claims priority of application No. 202010963896.9 (CN), filed on Sep. 14, 2020.
Prior Publication US 2022/0084881 A1, Mar. 17, 2022
Int. Cl. H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 49/02 (2006.01)
CPC H01L 21/76877 (2013.01) [H01L 21/76831 (2013.01); H01L 23/5223 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 28/60 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate, the substrate being provided with a conductive structure;
a first lower electrode and a second lower electrode sequentially stacked, the first lower electrode being located between the second lower electrode and the substrate, the first lower electrode being columnar, the second lower electrode being in a shape of a recess, and the first lower electrode being electrically connected to the conductive structure;
a first dielectric layer and a first upper electrode, the first dielectric layer covering a sidewall surface of the first lower electrode, and the first upper electrode being located on one side of the first dielectric layer away from the first lower electrode;
a second dielectric layer and a second upper electrode, the second dielectric layer covering an inner wall and a bottom surface of the second lower electrode, and the second upper electrode filling the recess of the second lower electrode; and
a support layer comprising a first support layer, a second support layer, the first support layer being located between bottoms of the first lower electrodes, the second support layer being located between tops of the first lower electrodes, and the second support layer between tops of the first lower electrodes having a different dimension along the direction of the surface of the substrate, wherein the second support layer between the tops of the first lower electrodes having a larger dimension along the direction of the surface of the substrate is in direct contact with the first upper electrode therebelow; and the second support layer between the tops of the first lower electrodes having a smaller dimension along the direction of the surface of the substrate is in direct contact with the first dielectric layer therebelow.