US 11,984,350 B2
Integrated circuit structure with backside interconnection structure having air gap
Li-Zhen Yu, New Taipei (TW); Huan-Chieh Su, Changhua County (TW); Lin-Yu Huang, Hsinchu (TW); Cheng-Chi Chuang, New Taipei (TW); and Chih-Hao Wang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Dec. 14, 2022, as Appl. No. 18/066,071.
Application 18/066,071 is a continuation of application No. 17/199,085, filed on Mar. 11, 2021, granted, now 11,551,969.
Claims priority of provisional application 63/082,018, filed on Sep. 23, 2020.
Prior Publication US 2023/0121408 A1, Apr. 20, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 23/532 (2006.01); H01L 23/535 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 21/7682 (2013.01) [H01L 21/0259 (2013.01); H01L 21/76805 (2013.01); H01L 21/76843 (2013.01); H01L 21/76895 (2013.01); H01L 23/5329 (2013.01); H01L 23/535 (2013.01); H01L 29/0665 (2013.01); H01L 29/41733 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a transistor over a substrate;
forming a front-side interconnection structure over the transistor;
after forming the front-side interconnection structure, removing the substrate;
after removing the substrate, forming a backside via to be electrically connected to the transistor;
depositing a dielectric layer to cover the backside via;
forming an opening in the dielectric layer to expose the backside via;
forming a spacer structure on a sidewall of the opening;
after forming a spacer structure, forming a conductive feature in the opening to be electrically connected to the backside via; and
after forming the conductive feature, forming an air gap in the spacer structure.