| CPC H01L 21/76802 (2013.01) [H01L 21/76829 (2013.01); H01L 23/562 (2013.01)] | 18 Claims |
|
1. A semiconductor device, comprising:
a semiconductor substrate including a chip region and an edge region around the chip region;
a lower dielectric layer on the semiconductor substrate;
an upper dielectric layer on the lower dielectric layer;
a chip pad on the lower dielectric layer of the chip region;
a redistribution chip pad that penetrates the upper dielectric layer on the chip region and is connected the chip pad;
a process monitoring structure on the edge region, the upper dielectric layer covering the process monitoring structure and including an opening spaced apart from the process monitoring structure and exposing a portion of the lower dielectric layer on the edge region;
dummy elements in the edge region and having an upper surface lower than an upper surface of the upper dielectric layer; and
a redistribution spacer on an inner wall of the opening of the upper dielectric layer, the redistribution spacer including the same metallic material as that of the redistribution chip pad,
wherein the dummy elements include a plurality of dummy redistribution patterns that penetrate the upper dielectric layer in the edge region.
|