CPC H01G 4/012 (2013.01) [H01G 4/12 (2013.01); H01G 4/228 (2013.01); H01L 21/31111 (2013.01); H01L 21/32139 (2013.01); H01L 28/60 (2013.01); H10N 30/302 (2023.02); H10N 30/501 (2023.02); H10N 30/508 (2023.02); H10N 30/872 (2023.02)] | 20 Claims |
1. An integrated chip comprising:
a first electrode;
a second electrode over the first electrode;
a dielectric structure sandwiched between the first electrode and the second electrode; and
a passivation layer over the second electrode and the dielectric structure, wherein the passivation layer comprises a first horizontal surface and a second horizontal surface vertically below a top surface of the passivation layer, wherein the first and second horizontal surfaces are disposed above a top surface of the dielectric structure and below a top surface of the second electrode, wherein outermost opposing sidewalls of the second electrode are spaced laterally between the first and second horizontal surfaces.
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