US 11,984,186 B2
Apparatuses and methods for repairing defective memory cells based on a specified error rate for certain memory cells
David Hulton, Seattle, WA (US); Tamara Schmitz, Scotts Valley, CA (US); Jonathan D. Harms, Meridian, ID (US); Jeremy Chritz, Seattle, WA (US); and Kevin Majerus, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Nov. 10, 2021, as Appl. No. 17/454,443.
Application 17/454,443 is a continuation of application No. 16/453,905, filed on Jun. 26, 2019, granted, now 11,183,266.
Prior Publication US 2022/0068430 A1, Mar. 3, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/00 (2006.01); G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 12/126 (2016.01); G06F 11/10 (2006.01); G06F 12/0813 (2016.01); G11C 11/408 (2006.01); G11C 11/418 (2006.01); G11C 29/04 (2006.01); G11C 29/44 (2006.01); H04L 61/2575 (2022.01)
CPC G11C 29/76 (2013.01) [G06F 3/0659 (2013.01); G06F 12/0246 (2013.01); G06F 12/126 (2013.01); G06F 11/1048 (2013.01); G06F 12/0813 (2013.01); G11C 11/408 (2013.01); G11C 11/418 (2013.01); G11C 29/04 (2013.01); G11C 29/44 (2013.01); G11C 29/4401 (2013.01); G11C 29/787 (2013.01); H04L 61/2575 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method comprising:
obtaining a memory access pattern associated with a plurality of memory access operations, the memory access pattern indicative of first regions of a memory associated with a high priority level that are accessed for data at a higher frequency than second regions of the memory associated with a lower priority level than the high priority level, wherein the high priority level is associated with a first maximum allowable bit error rate and the lower priority level is associated with a second maximum allowable bit error rate that is different than the first maximum allowable error rate;
generating a memory address map for the plurality of memory access operations based on the first regions of the memory and the second regions of the memory identified associated with the second maximum allowable bit error rate; and
providing the memory address map to a memory data register of the memory, the memory data register accessible by the memory for repairing at least one region of the second regions of the memory.