CPC G11C 29/46 (2013.01) [G06F 11/2094 (2013.01)] | 12 Claims |
1. An information handling system comprising:
a processor;
a memory communicatively coupled to the processor; and
a basic input/output system communicatively coupled to the processor and comprising a program of executable instructions configured to:
maintain a System Management Random Access Memory (SMRAM) test flag indicative of a requirement to test a designated region of memory configured as an SMRAM for use in a System Management Mode (SMM) mode of operation; and
during a Pre-Extensible Firmware Interface Initialization (PEI) phase of the basic input/output system, responsive to detecting that the SMRAM test flag is set:
test the designated region and responsive to detecting a memory fault:
map out the designated region and designate an additional region of the memory as a designated region for SMRAM; and
repeat testing of additional designated regions, mapping out of failed additional designated regions, and designating new additional regions of the memory until a designated region passes testing without memory fault; and
in response to detecting passage of testing without memory fault of a designated region comprising either of the first designated region or an additional region of the memory, configure the designated region for use as the SMRAM for the information handling system; and
responsive to a system management interrupt (SMI), configure the information handling system to enter the SMM, in which the SMRAM is configured as a separate address space dedicated for executing SMM code.
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