US 11,984,180 B2
Enabling or disabling on-die error-correcting code for a memory built-in self-test
Scott E. Schaefer, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 16, 2022, as Appl. No. 17/807,314.
Claims priority of provisional application 63/365,631, filed on Jun. 1, 2022.
Prior Publication US 2023/0395177 A1, Dec. 7, 2023
Int. Cl. G11C 29/00 (2006.01); G11C 29/10 (2006.01); G11C 29/42 (2006.01); G11C 29/44 (2006.01); G11C 29/46 (2006.01)
CPC G11C 29/42 (2013.01) [G11C 29/10 (2013.01); G11C 29/4401 (2013.01); G11C 29/46 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A memory device, comprising:
one or more components configured to:
read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device;
identify, based on the one or more bits, whether the memory built-in self-test is to be performed with on-die error-correcting code (ECC) disabled or with on-die ECC enabled,
wherein a single-bit error is capable of being detected by the memory built-in self-test when the on-die ECC is disabled but is not capable of being detected by the memory built-in self-test when the on-die ECC is enabled; and
perform the memory built-in self-test, and selectively test for one or more single-bit errors, based on identifying whether the memory built-in self-test is to be performed with the on-die ECC disabled or with the on-die ECC enabled.