US 11,984,178 B2
Methods and devices for flexible RAM loading
Gabriele Solcia, Mezzago (IT)
Assigned to STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed by STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed on Jan. 20, 2022, as Appl. No. 17/580,458.
Prior Publication US 2023/0230650 A1, Jul. 20, 2023
Int. Cl. G11C 29/36 (2006.01); G11C 7/10 (2006.01); G11C 29/12 (2006.01); G11C 29/46 (2006.01); H03K 19/173 (2006.01); H03K 19/20 (2006.01)
CPC G11C 29/36 (2013.01) [G11C 7/1036 (2013.01); G11C 29/1201 (2013.01); G11C 29/46 (2013.01); H03K 19/1737 (2013.01); H03K 19/20 (2013.01); G11C 2029/3602 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A flexible RAM loading device comprising:
a shift register comprising a first data section, a second data section, and a first shift-register selection bit;
a test register comprising a data section and a first test-register selection bit, the first test-register selection bit being loaded from the first shift-register selection bit; and
a first shift-register MUX comprising:
a first input coupled with an output of the first data section;
a second input coupled with a first external data pin;
an output coupled with an input of the second data section; and
a selection input coupled with the first test-register selection bit, the output of the first shift-register MUX depending the first test-register selection bit.