| CPC G11C 13/0033 (2013.01) [G11C 13/0004 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/003 (2013.01); G11C 13/004 (2013.01)] | 17 Claims |
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1. A nonvolatile memory apparatus comprising:
a memory cell coupled between a global bit line and a global word line;
a bit line control circuit configured to provide a first high voltage to the global bit line based on a read signal and to provide a second high voltage to the global bit line based on a first control signal, and configured to control a first current to flow through the global bit line based on the read signal and to control a second current to flow through the global bit line based on the first control signal;
a word line control circuit configured to provide a first low voltage to the global word line based on the read signal and to provide a second low voltage to the global word line based on a second control signal; and
a sense amplifier configured to sense a voltage level of the global bit line to determine whether snapback of the memory cell has occurred, and configured to generate the first and second control signals when the snapback of the memory cell has occurred,
wherein the second current is larger than the first current, and the second current comprises an amount of current capable of setting a resistance state of the memory cell to a low resistance state,
wherein the second high voltage has a higher voltage level than the first high voltage.
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