US 11,984,147 B2
Semiconductor device including sense amplifier and operation method of semiconductor device
Takanori Matsuzaki, Atsugi (JP); Tatsuya Onuki, Atsugi (JP); Yuki Okamoto, Isehara (JP); and Toshiki Hamada, Isehara (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Appl. No. 17/602,431
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
PCT Filed Apr. 15, 2020, PCT No. PCT/IB2020/053526
§ 371(c)(1), (2) Date Oct. 8, 2021,
PCT Pub. No. WO2020/217138, PCT Pub. Date Oct. 29, 2020.
Claims priority of application No. 2019-085084 (JP), filed on Apr. 26, 2019.
Prior Publication US 2022/0172766 A1, Jun. 2, 2022
Int. Cl. G11C 11/405 (2006.01); G11C 11/4091 (2006.01); G11C 11/56 (2006.01); H01L 29/786 (2006.01)
CPC G11C 11/405 (2013.01) [G11C 11/4091 (2013.01); G11C 11/5642 (2013.01); G11C 11/565 (2013.01); H01L 29/7869 (2013.01); H01L 29/78696 (2013.01); G11C 2211/5634 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a memory cell, a first reference cell, a second reference cell, a first sense amplifier, a second sense amplifier, a first circuit, a second circuit, a third circuit, a first switch, a second switch, a first wiring, a second wiring, a third wiring, and a fourth wiring,
wherein the first circuit comprises a first transistor,
wherein the second circuit comprises a second transistor,
wherein the third circuit comprises a third transistor,
wherein the memory cell is electrically connected to a gate of the first transistor,
wherein the first reference cell is electrically connected to a gate of the second transistor,
wherein the second reference cell is electrically connected to a gate of the third transistor,
wherein the first wiring is electrically connected to a first terminal of the first transistor, a first terminal of the first switch, and the first sense amplifier,
wherein the second wiring is electrically connected to a first terminal of the second transistor, a first terminal of the second switch, and the first sense amplifier,
wherein the third wiring is electrically connected to a second terminal of the first switch and the second sense amplifier,
wherein the fourth wiring is electrically connected to a first terminal of the third transistor, a second terminal of the second switch, and the second sense amplifier,
wherein the first circuit is configured to correct a threshold voltage of the first transistor,
wherein the second circuit is configured to correct a threshold voltage of the second transistor,
wherein the third circuit is configured to correct a threshold voltage of the third transistor,
wherein the first circuit is configured to output a first potential corresponding to a first signal output from the memory cell to the first wiring and the third wiring, when the first switch is in an on state,
wherein the second circuit is configured to output a second potential corresponding to a second signal output from the first reference cell to the second wiring, when the second switch is in an off state, and
wherein the third circuit is configured to output a third potential corresponding to a third signal output from the second reference cell to the fourth wiring, when the second switch is in an off state.