US 11,984,093 B2
Semiconductor device and electronic appliance
Jun Koyama, Kanagawa (JP); and Atsushi Umezaki, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Dec. 29, 2022, as Appl. No. 18/090,587.
Application 18/090,587 is a continuation of application No. 17/153,975, filed on Jan. 21, 2021, granted, now 11,545,105.
Application 17/153,975 is a continuation of application No. 16/599,283, filed on Oct. 11, 2019, granted, now 10,902,814, issued on Jan. 26, 2021.
Application 16/599,283 is a continuation of application No. 16/245,324, filed on Jan. 11, 2019, granted, now 10,446,103, issued on Oct. 15, 2019.
Application 16/245,324 is a continuation of application No. 15/935,150, filed on Mar. 26, 2018, granted, now 10,181,304, issued on Jan. 15, 2019.
Application 15/935,150 is a continuation of application No. 15/496,061, filed on Apr. 25, 2017, granted, now 9,934,747, issued on Apr. 3, 2018.
Application 15/496,061 is a continuation of application No. 15/175,189, filed on Jun. 7, 2016, granted, now 9,830,878, issued on Nov. 28, 2017.
Application 15/175,189 is a continuation of application No. 14/522,817, filed on Oct. 24, 2014, granted, now 9,368,519, issued on Jun. 14, 2016.
Application 14/522,817 is a continuation of application No. 14/147,647, filed on Jan. 6, 2014, granted, now 8,872,572, issued on Oct. 28, 2014.
Application 14/147,647 is a continuation of application No. 13/921,401, filed on Jun. 19, 2013, granted, now 8,624,656, issued on Jan. 7, 2014.
Application 13/921,401 is a continuation of application No. 12/879,610, filed on Sep. 10, 2010, granted, now 8,471,620, issued on Jun. 25, 2013.
Claims priority of application No. 2009-214848 (JP), filed on Sep. 16, 2009.
Prior Publication US 2023/0215396 A1, Jul. 6, 2023
Int. Cl. G09G 3/36 (2006.01); G11C 19/00 (2006.01); H01L 27/02 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H03K 17/687 (2006.01); H03K 19/00 (2006.01); H03K 19/0185 (2006.01)
CPC G09G 3/3677 (2013.01) [G09G 3/3674 (2013.01); G11C 19/00 (2013.01); H01L 27/0207 (2013.01); H01L 27/1214 (2013.01); H01L 27/1225 (2013.01); H01L 27/124 (2013.01); H01L 29/7869 (2013.01); H03K 17/687 (2013.01); H03K 19/0013 (2013.01); H03K 19/018557 (2013.01); H03K 19/018571 (2013.01); G09G 2310/0251 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/0289 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A liquid crystal display device comprising:
a first scan line driver circuit configured to drive a first gate signal line;
a second scan line driver circuit configured to drive a second gate signal line; and
a pixel portion between the first scan line driver circuit and the second scan line driver circuit, the pixel portion comprising a pixel,
wherein at least one of the first scan line driver circuit and the second scan line driver circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, one of a source and a drain of the seventh transistor, and a first wiring,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein a gate of the first transistor is electrically connected to the one of the source and the drain of the third transistor and the one of the source and the drain of the fourth transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the seventh transistor and a third wiring,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the sixth transistor,
wherein a gate of the second transistor is electrically connected to a gate of the fourth transistor, the one of the source and the drain of the fifth transistor, and the one of the source and the drain of the sixth transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to a fifth wiring,
wherein a gate of the fifth transistor is electrically connected to a sixth wiring,
wherein a gate of the seventh transistor is electrically connected to a seventh wiring,
wherein the second wiring is configured to supply a first clock signal,
wherein the third wiring is configured to supply a first power supply voltage,
wherein the fifth wiring is configured to supply a second power supply voltage which is higher than the first power supply voltage, and
wherein the sixth wiring is configured to supply a second clock signal.