CPC G09G 3/2092 (2013.01) [G09G 3/32 (2013.01); G09G 3/20 (2013.01); G09G 3/3208 (2013.01); G09G 3/3266 (2013.01); G09G 3/3275 (2013.01); G09G 3/3607 (2013.01); G09G 2310/0218 (2013.01); G09G 2310/0248 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0275 (2013.01); G09G 2310/061 (2013.01); G09G 2310/062 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/0261 (2013.01); G09G 2320/0626 (2013.01); G09G 2320/064 (2013.01); G09G 2320/0646 (2013.01); G09G 2340/16 (2013.01)] | 20 Claims |
1. A display device comprising:
a display panel including a plurality of pixels;
a controller configured to generate a second data enable signal and second image data by performing a data processing operation on first image data synchronized with a first data enable signal, and to generate an output data enable signal and output image data by performing a black data insertion operation for the second data enable signal and the second image data; and
a data driver configured to provide data signals to the plurality of pixels based on the output data enable signal and the output image data,
wherein the controller obtains a delay time between at least one of the first data enable signal and the second data enable signal or the first image data and the second image data, determines a number of subsequent pulses of the output data enable signal which are to be output during a period from one time point within a frame period to an end time point of the frame period, and adjusts a cycle of the subsequent pulses of the output data enable signal based on the delay time and the number of the subsequent pulses.
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