US 11,983,622 B2
High-density neuromorphic computing element
Borna J. Obradovic, Leander, TX (US); Titash Rakshit, Austin, TX (US); and Mark S. Rodder, Dallas, TX (US)
Assigned to Samsung Electronics Co., Ltd., Yongin-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 17, 2023, as Appl. No. 18/111,471.
Application 17/094,356 is a division of application No. 15/488,419, filed on Apr. 14, 2017, granted, now 10,860,923, issued on Dec. 8, 2020.
Application 18/111,471 is a continuation of application No. 17/094,356, filed on Nov. 10, 2020, granted, now 11,586,901.
Claims priority of provisional application 62/437,016, filed on Dec. 20, 2016.
Prior Publication US 2023/0206053 A1, Jun. 29, 2023
Int. Cl. G06N 3/065 (2023.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H01L 29/808 (2006.01); H10B 41/30 (2023.01)
CPC G06N 3/065 (2023.01) [H01L 29/40114 (2019.08); H01L 29/42324 (2013.01); H01L 29/66825 (2013.01); H01L 29/7881 (2013.01); H01L 29/8083 (2013.01); H10B 41/30 (2023.02)] 15 Claims
OG exemplary drawing
 
1. A neuromorphic device, comprising:
a substrate;
a first floating-gate transistor on the substrate;
a second floating-gate transistor on the first floating-gate transistor in a stacking direction;
a gate contact connected to control gates of the first and second floating-gate transistors;
a first source-drain contact connected to a first end of a channel of the first floating-gate transistor; and
a second source-drain contact connected to a second end of the channel of the first floating-gate transistor and to a first end of a channel of the second floating-gate transistor, a portion of the second source-drain contact overlapping with a floating gate of the first floating-gate transistor and a floating gate of the second floating gate transistor in the stacking direction.