US 11,983,605 B2
Partitioned template matching and symbolic peephole optimization
Sergey Bravyi, Ossining, NY (US); Shaohan Hu, Yorktown Heights, NY (US); Dmitri Maslov, New Canaan, CT (US); and Ruslan Shaydulin, Anderson, SC (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Oct. 28, 2020, as Appl. No. 17/082,844.
Prior Publication US 2022/0129411 A1, Apr. 28, 2022
Int. Cl. G06N 10/20 (2022.01); G06F 30/323 (2020.01); G06F 30/3308 (2020.01); G06F 30/337 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01); G06N 10/00 (2022.01); G06N 10/80 (2022.01)
CPC G06N 10/20 (2022.01) [G06F 30/323 (2020.01); G06N 10/00 (2019.01); G06F 30/3308 (2020.01); G06F 30/337 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01); G06N 10/80 (2022.01)] 20 Claims
OG exemplary drawing
 
9. A computer-implemented method, comprising:
performing, by a device operatively coupled to a processor, using a library of templates comprising gates, template matching on a Clifford circuit associated with a set of qubits; and
partitioning, by the device and prior to the template matching, the Clifford circuit into a computation stage, a Pauli stage, and a SWAP stage, wherein the template matching is performed on the computation stage, and wherein:
the computation state comprises all Hadamard gates, all Phase gates, and all Controlled NOT gates of the Clifford circuit, and does not comprise any Pauli gates and any SWAP gates of the Clifford circuit;
the Pauli stage comprises all Pauli gates of the Clifford circuit, and does not comprise any Hadamard gates, any Phase gates, any Controlled NOT gates, and any SWAP gates of the Clifford circuit; and
the SWAP stage comprises all SWAP gates of the Clifford circuit, and does not comprise any Hadamard gates, any Phase gates, any Controlled NOT gates, and any Pauli gates of the Clifford circuit.