US 11,983,530 B2
Reconfigurable digital signal processing (DSP) vector engine
Sumeet Singh Nagi, Los Angeles, CA (US); Farhana Sheikh, Portland, OR (US); Scott Jeremy Weber, Piedmont, CA (US); and Uneeb Yaqub Rathore, Los Angeles, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 27, 2020, as Appl. No. 16/833,164.
Prior Publication US 2020/0225947 A1, Jul. 16, 2020
Int. Cl. G06F 9/30 (2018.01); G06F 7/48 (2006.01); G06F 7/49 (2006.01); G06F 7/50 (2006.01); G06F 7/523 (2006.01); G06F 9/50 (2006.01); G06F 17/16 (2006.01)
CPC G06F 9/3001 (2013.01) [G06F 7/4806 (2013.01); G06F 7/49 (2013.01); G06F 7/50 (2013.01); G06F 7/523 (2013.01); G06F 9/5027 (2013.01); G06F 17/16 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a first circuit;
interface circuitry; and
an integrated accumulator coupled to the first circuit through the interface circuitry, wherein the integrated accumulator is configurable to perform a complex number operation at a first time and to perform a real number operation at a second time, wherein the integrated accumulator performs the real number operation using first real type data as an input and generates second real type data as an output, wherein the integrated accumulator comprises a plurality of multipliers and a plurality of adders, wherein the integrated accumulator has a reprogrammable data width, and wherein a data width of data processed using the complex number operation or the real number operation is different from a data width of the interface circuitry.