| CPC G06F 30/394 (2020.01) [H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); H01L 27/0207 (2013.01); H01L 27/11807 (2013.01); H01L 2027/11887 (2013.01)] | 20 Claims |
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1. A method of fabricating an integrated circuit, the method comprising:
placing a first set of conductive feature patterns on a first level, the first set of conductive feature patterns extending in a first direction, and each conductive feature pattern of the first set of conductive feature patterns being separated from each other in a second direction different from the first direction;
placing a second set of conductive feature patterns on a second level different from the first level, the second set of conductive feature patterns extending in the second direction, overlapping the first set of conductive feature patterns, and each conductive feature pattern of the second set of conductive feature patterns being separated from each other in the first direction;
placing a first set of via patterns between the second set of conductive feature patterns and the first set of conductive feature patterns, and each via pattern of the first set of via patterns being located where each conductive feature pattern of the second set of conductive feature patterns overlaps each conductive feature pattern of the first set of conductive feature patterns;
placing a third set of conductive feature patterns on a third level different from the first level and the second level, the third set of conductive feature patterns extending in the first direction, overlapping the second set of conductive feature patterns, covering a portion of the first set of conductive feature patterns, each conductive feature pattern of the third set of conductive feature patterns being separated from each other in the second direction; and
placing a second set of via patterns between the third set of conductive feature patterns and the second set of conductive feature patterns, and each via pattern of the second set of via patterns being located where each conductive feature pattern of the third set of conductive feature patterns overlaps each conductive feature pattern of the second set of conductive feature patterns;
placing a first power rail pattern on the first level, the first power rail pattern extending in the first direction, and corresponding to a first power rail configured to supply a first supply voltage; and
placing a second power rail pattern on the first level, the second power rail pattern extending in the first direction, and corresponding to a second power rail configured to supply a second supply voltage different from the first supply voltage, the second power rail pattern being separated from the first power rail pattern in the second direction,
wherein at least the first set of conductive feature patterns, the second set of conductive feature patterns or the third set of conductive feature patterns is between the first power rail pattern and the second power rail pattern;
wherein at least one of the above patterns is stored on a non-transitory computer-readable medium, and at least one of the above operations is performed by a hardware processor; and
manufacturing the integrated circuit based on at least one of the above patterns of the integrated circuit.
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