at an end point of physical design synthesis optimization flow for a putative integrated circuit design having a plurality of nets, identifying at least one congested region in said putative integrated circuit design;

identifying those of said nets of said putative integrated circuit design traversing through said at least one congested region, to obtain a plurality of candidate nets for demotion;

demoting a plurality of selected nets, selected from said plurality of candidate nets for demotion, from an upper routing layer of said putative integrated circuit design to a lower routing layer of said putative integrated circuit design, wherein at least some of said plurality of selected nets experience a loss of timing quality of result after said demoting; and

limiting negative impact to timing closure of said putative integrated circuit design by selecting said plurality of selected nets from said plurality of candidate nets for demotion and by refraining from demotion based on a constraint of not introducing any new net timing slacks below a predetermined limit to said putative integrated circuit design during said demoting, wherein said not introducing any new net timing slacks below said predetermined limit to said putative integrated circuit design during said demoting comprises not demoting a given one of said plurality of candidate nets for demotion responsive to determining that: