| CPC G06F 30/392 (2020.01) [G06F 30/373 (2020.01); G06F 30/394 (2020.01); G06F 2111/20 (2020.01)] | 20 Claims |
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1. A semiconductor device comprising:
a transistor layer that overlays a substrate layer;
M*1st conductors extending in a first direction, being in a first layer of metallization (M*1st layer) that overlays the transistor layer and being aligned correspondingly along alpha tracks,
the M*1st conductors including first and second input pins aligned to different corresponding ones of the alpha tracks and representing corresponding inputs of a cell region, the cell region representing at least part of a circuit in the semiconductor device; and
M*2nd conductors extending in a second direction perpendicular to the first direction, being in a second layer of metallization (M*2nd layer) that overlays the M*1st layer and being aligned correspondingly along beta tracks, and the M*2nd conductors including at least one power grid (PG) segment and one or more of an output pin or a routing segment; and
each of the first and second input pins having a length in the first direction sufficient to accommodate at most two access points;
each of the access points of the first and second input pins being aligned to a corresponding different one of first, second, third and fourth ones of beta tracks (first to fourth beta tracks); and
the PG segment being aligned with one of the first to fourth beta tracks.
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