US 11,983,474 B1
Connecting random variables to coverage targets using an ensemble of static analysis, dynamic analysis and machine learning and guided constraint solving of the random variables during simulation of an integrated circuit
Parijat Biswas, Benniganahalli (IN); Badri Gopalan, Cupertino, CA (US); Enzhi Ni, Shanghai (CN); Danish Jawed, Indirapuram (IN); Ying Chen, Shanghai (CN); and Jiang Chen, Shanghai (CN)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Dec. 23, 2021, as Appl. No. 17/561,371.
Claims priority of provisional application 63/138,025, filed on Jan. 15, 2021.
Claims priority of provisional application 63/129,940, filed on Dec. 23, 2020.
Int. Cl. G06F 30/30 (2020.01); G01R 31/3183 (2006.01); G06F 30/323 (2020.01); G06F 30/3308 (2020.01)
CPC G06F 30/3308 (2020.01) [G01R 31/31835 (2013.01); G01R 31/318357 (2013.01); G06F 30/323 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method for verifying an integrated circuit (IC) design described in a hardware description or hardware verification language (HDHVL), the method comprising:
identifying connections between random variables and coverage areas of the IC design, as described in HDHVL code, the connections being identified by determining which coverage areas of the IC design will be influenced during simulation by which random variables, such that each connection identifies, at least, (i) a respective random variable and (ii) a coverage area of the IC design that will be influenced by the respective random variable during simulation;
storing the identified connections in a database; and
using, by a processor connections retrieved from the database to simulate and verify the coverage areas of the IC design.