US 11,983,410 B2
Method optimizing DQ calibration pattern for memory device and computing system performing same
Yongseob Kim, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Nov. 18, 2021, as Appl. No. 17/530,226.
Claims priority of application No. 10-2021-0025491 (KR), filed on Feb. 25, 2021.
Prior Publication US 2022/0269419 A1, Aug. 25, 2022
Int. Cl. G06F 3/06 (2006.01); G06F 13/16 (2006.01); G06N 20/00 (2019.01); G11C 7/10 (2006.01); G11C 7/20 (2006.01)
CPC G06F 3/0611 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0673 (2013.01); G06F 13/1689 (2013.01); G06N 20/00 (2019.01); G11C 7/1078 (2013.01); G11C 7/20 (2013.01); G11C 2207/2254 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method optimizing DQ calibration patterns for a memory device including data input/output (I/O) pins, the method comprising:
communicating a training command to the memory device;
performing a training operation on each of the data I/O pins using a first training pattern having a first condition and a second training pattern having a second condition to generate a training operation result, wherein the first condition is characterized by adjacent data I/O pins among the data I/O pins providing data signals with different phases, and the second condition is characterized by adjacent data I/O pins providing data signals having a same phase; and
aligning a data strobe signal with data signals provided from the data I/O pins in response the training operation result,
wherein the different phases are opposite phases.