US 11,983,408 B2
Ballooning for multi-tiered pooled memory
Rasika Subramanian, Hillsboro, OR (US); Lidia Warnes, Roseville, CA (US); Francesc Guim Bernat, Barcelona (ES); Mark A. Schmisseur, Phoenix, AZ (US); and Durgesh Srivastava, Cupertino, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 3, 2023, as Appl. No. 18/142,942.
Application 18/142,942 is a continuation of application No. 16/914,124, filed on Jun. 26, 2020, granted, now 11,681,439.
Prior Publication US 2023/0333738 A1, Oct. 19, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0608 (2013.01) [G06F 3/0631 (2013.01); G06F 3/0665 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic apparatus, comprising:
one or more substrates; and
logic coupled to the one or more substrates, the logic to:
allocate a first memory portion to a first application as a combination of a main memory of a compute node and re-allocatable pooled memory, wherein the re-allocatable pooled memory is shared between multiple compute nodes, and
manage a first memory allocation amount associated with the first memory portion based on two or more memory tiers associated with the main memory and the re-allocatable pooled memory.