a substrate having a display region including a pixel region and a first peripheral region surrounding the pixel region, a second peripheral region that is spaced apart from the display region, and a bending region that is interposed between the display region and the second peripheral region;

a buffer layer disposed on the substrate, the buffer layer having a first removed region exposing a portion of an upper surface of the substrate, the first removed region overlapping, the bending region, a portion of the first peripheral region, and a portion of the second peripheral region;

a plurality of pixel structures disposed in the pixel region on the buffer layer;

an insulation layer structure including a plurality of insulation layers disposed on the buffer layer, the insulation layer structure having a second removed region exposing the first removed region and a top surface of a portion of the buffer layer that is disposed adjacent to the first removed region, the top surface being a surface of the buffer layer that faces away from, and is farthest from, the substrate;

a fan-out wiring disposed in the insulation layer structure, the fan-out wiring including a first fan-out wiring disposed in the first peripheral region and a second fan-out wiring disposed in the second peripheral region;

a first planarization layer disposed in the first peripheral region disposed adjacent to the bending region, the bending region, and the second peripheral region disposed adjacent to the bending region on the substrate; and

a connection electrode disposed on the first planarization layer, the connection electrode being electrically connected to the fan-out wiring.