US 11,983,140 B2
Efficient deconfiguration of a reconfigurable data processor
Manish K. Shah, Austin, TX (US); Ram Sivaramakrishnan, San Jose, CA (US); Mark Luttrell, Cedar Park, TX (US); David B. Jackson, Dana Point, CA (US); Raghu Prabhakar, Sunnyvale, CA (US); Sumti Jairath, Santa Clara, CA (US); Gregory Frederick Grohoski, Bee Cave, CA (US); and Pramod Nataraja, San Jose, CA (US)
Assigned to SambaNova Systems, Inc., Palo Alto, CA (US)
Filed by SambaNova Systems, Inc., Palo Alto, CA (US)
Filed on Nov. 22, 2021, as Appl. No. 17/533,058.
Application 17/533,058 is a continuation of application No. 16/198,086, filed on Nov. 21, 2018, granted, now 11,188,497.
Prior Publication US 2022/0083499 A1, Mar. 17, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/24 (2006.01); G06F 9/445 (2018.01); G06F 13/364 (2006.01); G06F 15/78 (2006.01); G06F 8/65 (2018.01); G06F 9/4401 (2018.01)
CPC G06F 15/7871 (2013.01) [G06F 9/44505 (2013.01); G06F 13/364 (2013.01); G06F 8/65 (2013.01); G06F 9/4411 (2013.01)] 27 Claims
OG exemplary drawing
 
1. A reconfigurable data processor, comprising:
a bus system;
an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of sub-files of configuration data particular to corresponding configurable units; and
a configuration unload controller connected to the bus system, including logic to execute an array configuration unload process, including distributing a command to a plurality of the configurable units in the array to unload the unit files particular to the corresponding configurable units, the unit files each comprising a plurality of ordered sub-files, receiving sub-files via the bus system from the array of configurable units, and assembling an unload configuration file by arranging the received sub-files in memory according to the configurable unit of the unit file of which the sub-file is a part, and the order of the sub-file in the unit file.