US 11,983,121 B1
Cache memory device and method for implementing cache scheduling using same
Do Hun Kim, Yongin-si (KR); Keebum Shin, Seongnam-si (KR); and Kwangsun Lee, Yongin-si (KR)
Assigned to METISX CO., LTD., Yongin-si (KR)
Filed by METISX CO., LTD., Yongin-si (KR)
Filed on Nov. 15, 2023, as Appl. No. 18/510,232.
Claims priority of application No. 10-2023-0051364 (KR), filed on Apr. 19, 2023.
Int. Cl. G06F 12/123 (2016.01); G06F 12/0895 (2016.01)
CPC G06F 12/123 (2013.01) [G06F 12/0895 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A cache memory device comprising:
a command reception unit for packetizing each of read commands and write commands and classifying each of the read commands and the write commands as an even number or an odd number based on an address of each packet;
a cache scheduler comprising a first reorder scheduling queue for receiving commands classified as even numbers from the command reception unit and scheduling the commands classified as even numbers for cache memory accesses and a second reorder scheduling queue for receiving commands classified as odd numbers from the command reception unit and scheduling the commands classified as odd numbers for cache memory accesses; and
an access execution unit for performing cache memory accesses via a cache tag to scheduled commands classified as even numbers and scheduled commands classified as odd numbers,
wherein the access execution unit processes a first command and a second command at the same time if one of the two commands is a read command and the other of the two commands is a write command, wherein the first command is a command whose processing turn has arrived among the scheduled commands classified as even numbers and the second command is a command whose processing turn has arrived among the scheduled commands classified as odd numbers.